1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor fabrication supervision and optimization.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, ie., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an improved monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Among the parameters it would be useful to monitor and control are interlayer dielectric layer thickness variations. Typically, the total dielectric film thickness between metal layers is comprised of dielectric materials formed in two different deposition steps, e.g., a high density plasma process is used to fill the gaps between metal lines, and a silicon dioxide cap layer is formed by a deposition process using TEOS. After the insulation layers are formed, a chemical mechanical planarization process (CMP) is performed. The CMP process is performed to ensure that the proper post-polish thickness of the total dielectric material has been achieved. Chemical-mechanical planarization (CMP) is a process designed to remove and/or eliminate unwanted surface or xe2x80x9ctopographicxe2x80x9d features of a process layer. Chemical-mechanical planarization (CMP) typically involves physically polishing the surface or xe2x80x9ctopographyxe2x80x9d of a process layer in the presence of a chemically reactive slurry to remove and/or eliminate the unwanted surface or topographic features of the process layer. Using this technique, the CMP process must account for thickness variations resulting from two deposition processes. This may result in increased use of CMP processing resources and increased manufacturing time. This may lead to inaccuracies and complications in the manufacturing processes.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided that comprises forming a first dielectric layer on a workpiece, measuring a thickness of the first dielectric layer, and forming a second dielectric layer above the first dielectric layer, the second dielectric layer being formed to a thickness that is determined based upon the measured thickness of the first dielectric layer. Other embodiments of the invention will be understood by those skilled in the art after a complete reading of the present application.